1. Field of the Invention
The present invention relates to a semiconductor device having a bipolar structure, and more particularly, it relates to an improvement for compatibly reducing a saturation voltage and a fall time.
2. Description of the Background Art
Generally known is a semiconductor device comprising a semiconductor body, a pair of main electrodes which are connected to a pair of major surfaces of the semiconductor body, and a bipolar structure, formed in the semiconductor body, consisting of p-type and n-type semiconductor layers which are alternately stacked in three layers along the major surfaces. An IGBT, an EST (emitter switched thyristor), an MCT (MOS controlled thyristor), an SIT and a GTO are typical examples thereof.
FIG. 36 is a front sectional view showing the structure of a conventional n-channel IGBT. In a general IGBT, a number of IGBT elements (hereinafter referred to as unit cells) are connected in parallel with each other. FIG. 36 is a sectional view showing a single unit cell. In this IGBT 151, an n-type buffer layer 2 and an n-type semiconductor layer 3 which is exposed on an upper major surface of a semiconductor body 12 are successively stacked on an upper major surface of a p-type semiconductor layer 1 which is exposed on a lower major surface of the semiconductor body 12. When the rated voltage is 600 V, the n-type semiconductor layer 3 has an n-type impurity concentration of about 2.times.10.sup.14 cm.sup.-3, while the buffer layer 2 is set at an n-type impurity concentration of about 1.times.10.sup.17 cm.sup.-3, which is higher than that of the n-type semiconductor layer 3.
Further, a p-type base layer 4 is selectively formed on an upper major surface portion of the n-type semiconductor layer 3. A pnp bipolar structure is formed by the p-type semiconductor layer 1, the n-type semiconductor layers 2 and 3 and the p-type base layer 4. Further, an n-type emitter region 5 is selectively formed on an upper major surface portion of the p-type base layer 4. On a channel region 6 which is an upper major surface portion of the p-type base layer 4 held by the n-type semiconductor layer 3 and the n-type emitter region 5, a gate electrode 8 is provided to be opposed thereto through a gate insulating film 7.
In addition, an emitter electrode 9 which is a first main electrode is formed on the upper major surface of the semiconductor body 12, to be electrically connected to both of the p-type base layer 4 and the n-type emitter region 5. On the other hand, a collector electrode 10 which is a second main electrode is electrically connected to the lower major surface of the semiconductor body 12, i.e., that of the p-type semiconductor layer 1.
An operation of this conventional device 151 is now described. First, a prescribed collector voltage V.sub.CE is applied across the emitter electrode 9 and the collector electrode 10. A gate voltage V.sub.GE exceeding a threshold value which is specific to the device is applied across the emitter electrode 9 and the gate electrode 8 at this time, whereby the channel region 6 of the p-type base layer 4 which is in proximity to the gate electrode 8 is reversed to an n-type, and an n-type channel is formed in the channel region 6.
Through this channel, electrons serving as carriers are injected from the emitter electrode 9 into the n-type semiconductor layer 3. The p-type semiconductor layer 1 and the n-type semiconductor layer 3 are forward-biased by the injected electrons, whereby holes serving as carriers are injected from the p-type semiconductor layer 1 into the n-type semiconductor layer 3. Consequently, the resistance of the n-type semiconductor layer 3 is remarkably reduced, and a main current flowing from the collector electrode 10 to the emitter electrode 9, i.e., a collector current I.sub.C, reaches a high value. Namely, the device enters a conducting state (is turned on). Thus, the resistance of the n-type semiconductor layer 3 is reduced by the injection of the holes from the p-type semiconductor layer 1 in the IGBT.
The resistance across the emitter electrode 9 and the collector electrode 10 in the ON state of the device is called ON-state resistance. In general, such ON-state resistance is evaluated through the collector voltage V.sub.CE (called a saturation collector voltage V.sub.CE (sat)) which appears when the collector current I.sub.C is at a rated current value. In general, the rated current of the IGBT is typically about 50 to 200 A/cm.sup.2. The saturation voltage V.sub.CE (sat), which causes power loss at an ON time, is preferably minimized.
Under a state of applying the gate voltage V.sub.GE of a constant magnitude, limitation of a constant amount corresponding to the gate voltage V.sub.GE is added to the flow rate of electrons flowing in the channel region 6 when the collector voltage V.sub.CE is increased. Therefore, the collector current I.sub.C flowing through the device is saturated at a constant value (called a saturation collector current I.sub.C (sat)) corresponding to the gate voltage V.sub.GE.
The buffer layer 2 which is in contact with the p-type semiconductor layer 1 is adapted to control the amount of the holes injected from the p-type semiconductor layer 1. Since the buffer layer 2 has a high n-type impurity concentration, the holes injected from the p-type semiconductor layer 1 readily recombine with the electrons of the buffer layer 2. Thus, the saturation collector current I.sub.C (sat) is reduced due to the provision of the buffer layer 2. As the saturation collector current I.sub.C (sat) is reduced, the device is hardly broken upon short-circuiting of a load. On the other hand, the ON-state resistance is increased due to the provision of the buffer layer 2. Thus, the saturation collector current I.sub.C (sat) and the ON-state resistance are comprehensively optimized by properly adjusting the thickness and the impurity concentration of the buffer layer 2.
When the gate voltage V.sub.GE is reduced to zero or a reverse bias (negative value) from the value exceeding the threshold value while applying the collector voltage V.sub.CE of the prescribed magnitude, the channel region 6 which has been reversed to the n-type returns to the original p-type. Consequently, the injection of the electrons from the emitter electrode 9 is stopped. Thus, the injection of the holes from the p-type semiconductor layer 1 is also stopped.
Thereafter the electrons and the holes which have been stored in the n-type semiconductor layer 3 (and the buffer layer 2) are collected in the collector electrode 10 and the emitter electrode 9 respectively, or reduced by recombining with each other, to finally disappear. At this time, the holes are reduced at a lower rate than the electrons, whereby a hole current passing into the emitter electrode 9 mainly causes the so-called tail current which appears in the collector current I.sub.C. A time required for attenuation of the collector current I.sub.C (generally defined by a time required for attenuating the collector current I.sub.C from 90% of I.sub.C in an ON-state to 10%) is called a fall time t.sub.f. The fall time t.sub.f is preferably minimized, as a matter of course.
The buffer layer 2 is also adapted to prevent a depletion layer extending from the p-type base layer 4 from reaching the p-type semiconductor layer 1 and allowing conduction between the p-type semiconductor layer 1 and the p-type base layer 4 (called "punch-through") when the collector voltage V.sub.CE is applied to the IGBT 151 up to a value which is close to a breakdown voltage, thereby improving the withstand voltage of the device.
In a general IGBT including the device 151 shown in FIG. 36, a trade-off relation is present between a requirement for reduction of the saturation voltage V.sub.CE (sat) and that for reduction of the fall time t.sub.f. In recent years, therefore, attempts for compatibly improving both of these requirements have been energetically advanced. Such an improvement has been mainly made by refining a MOS structure which is formed along the upper major surface of the semiconductor body 12 in the IGBT 151, i.e., the structure formed by the n-type semiconductor layer 3, the p-type base layer 4 and the n-type emitter region 5.
The inventor has presented an IGBT having a trench gate shown in a front sectional view of FIG. 37, in a meeting of a scientific society held in 1994. This IGBT 152 is provided with a groove 31 which opens on an upper major surface of a semiconductor body 12 and passes through a p-type base layer 4 and an n-type emitter region 5, to reach an n-type semiconductor layer 3. Further, a gate electrode 33 consisting of polysilicon is buried in the groove 31, through a gate insulating film 32. In this device 152, a region 35 of the p-type base layer 4 which is opposed to the gate electrode 33 serves as a channel region.
In the device 152, refinement of the MOS structure has been remarkably advanced due to the trench gate type of the MOS structure. Consequently, improvement of the saturation voltage V.sub.CE (sat) and the fall time t.sub.f has been advanced. Thus, compatible improvement of the saturation voltage V.sub.CE (sat) and the fall time t.sub.f in the IGBT has been mainly promoted by improving the MOS structure. However, the improvement of the MOS structure is regarded as reaching the limit by the employment of the trench gate structure.
On the other hand, the inventor has disclosed an IGBT which can compatibly improve the saturation voltage V.sub.CE (sat) and SOA (Safe Operation Area) by improving a portion different from the MOS structure as shown in a front sectional view of FIG. 38, in Japanese Patent Laying-Open No. 6-204481 (1994). In this device 153, a high concentration n-type semiconductor region 21 having a high n-type impurity concentration of about 1.times.10.sup.18 to 1.times.10.sup.21 cm.sup.-3 is selectively formed in a buffer layer 2. The n-type impurity concentration of the buffer layer 2 is set at a lower value of about 5.times.10.sup.14 to 1.times.10.sup.17 cm.sup.-3.
In this device 153, it is expected that not only the saturation voltage V.sub.CE (sat) and SOA are compatibly improved as compared with a device having the same MOS structure, but the saturation voltage V.sub.CE (sat) and the fall time t.sub.f can also be compatibly improved. Namely, it is expected that the device 153 achieves a breakthrough about the limit in improvement of the MOS structure, and prepares a way for further improving the saturation voltage V.sub.CE (sat) and the fall time t.sub.f. In the device 153, however, the shape of the high concentration n-type semiconductor region 21 is not optimized in view of compatible improvement of the saturation compatible improvement of the saturation voltage V.sub.CE (sat) and the fall time t.sub.f, and hence latent ability of the device 153 has not been sufficiently brought out.